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Statistics on systemverilog-design-patterns

Number of watchers on Github 19
Number of open issues 0
Main language SystemVerilog
Average time to merge a PR about 6 hours
Open pull requests 0+
Closed pull requests 0+
Last commit over 4 years ago
Repo Created over 4 years ago
Repo Last Updated 4 months ago
Size 40 KB
Organization / Authortenthousandfailures
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