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lowrisc-chip

The root repo for lowRISC project and FPGA demos.

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Statistics on lowrisc-chip

Number of watchers on Github 241
Number of open issues 16
Average time to close an issue about 2 months
Main language SystemVerilog
Average time to merge a PR 3 days
Open pull requests 1+
Closed pull requests 4+
Last commit almost 3 years ago
Repo Created over 5 years ago
Repo Last Updated over 2 years ago
Size 3.55 MB
Homepage http://www.lowris...
Organization / Authorlowrisc
Latest Releasev0.5-rc2
Contributors2
Page Updated
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lowRISC chip

The root git repo for lowRISC development and FPGA demos.

master status: master build status

update status: update build status

dev status: dev build status

Current version: Release version 0.4 (05-2017) --- lowRISC with tagged memory and minion core

To download the repo:

git clone -b minion-v0.4 --recursive https://github.com/lowrisc/lowrisc-chip.git

For the previous release:

################
# Version 0.3: lowRISC with a trace debugger (07-2016)
################
git clone -b debug-v0.3 --recursive https://github.com/lowrisc/lowrisc-chip.git

################
# Version 0.2: untethered lowRISC (12-2015)
################
git clone -b untether-v0.2 --recursive https://github.com/lowrisc/lowrisc-chip.git

################
# Version 0.1: tagged memory (04-2015)
################
git clone -b tagged-memory-v0.1 --recursive https://github.com/lowrisc/lowrisc-chip.git

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lowrisc-chip open issues Ask a question     (View All Issues)
  • about 4 years The future is many core
  • about 4 years Using open source graphics processor adds lowrisc
  • about 4 years Generic bootloader
  • about 4 years Find a cool way that the system id is the git commit hash
  • about 4 years Set MAM addresses and sizes from chip_top
  • over 4 years Issues to dealt with later
lowrisc-chip open pull requests (View All Pulls)
  • Jenkins dsl
lowrisc-chip list of languages used
lowrisc-chip latest release notes
v0.5-rc2 Ethernet lowrisc release

These are the pre-built executables to go with the ethernet release of the lowrisc release for the Nexys4-DDR FPGA board. It provides access to networking, remote login via ssh, compilation locally via the riscv-poky distribution, as well as improved performance with a rewritten SD-card Verilog interface and Linux driver. Remote booting and Network filing system root is offered as well as standalone use with VGA screen and USB keyboard. Admittedly performance is modest relative to a modern workstation, however many areas of optimisation are possible before commiting to a chip.

minion-v0.4-rc1 Minion-v0.4 pre-release binaries for updating documentation

This is the release candidate code freeze for minion-v0.4. Use at your own risk.

v0.3 lowRISC Debug Release

This is the lowRISC release v0.3, which mainly introduces the debug infrastructure. You can find a tutorial for the release here.

We use this release on Github to provide you prebuilt FPGA bitstreams and Linux. Please refer to the tutorial how to use them.

  • boot.bin The boot image including bbl, vmlinux and init ramdisk.
  • nexys4ddr_bram_boot.riscv The BRAM image to load boot.bin from SD to DDR.
  • nexys4ddr_bram_jump.riscv The BRAM image to directly jump to DDR.
  • nexys4ddr_fpga_debug.bit The FPGA bitstream with a trace debugger.
  • nexys4ddr_fpga_standalone.bit The FPGA bitstream without a trace debugger.
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