Open source projects in SystemVerilog

  • tenthousandfailures/systemverilog-design-patterns

    ☕SystemVerilog   ★7 stars   ⚠0 open issues   ⚭1 contributors   ☯almost 3 years old  
  • genome/pindel

    Pindel can detect breakpoints of large deletions, medium sized insertions, inversions, tandem duplications and other structural variants at single-based resolution from next-gen sequence data. It uses a pattern growth approach to identify the breakpoints of these variants from paired-end short reads.

    ☕SystemVerilog   ★84 stars   ⚠59 open issues   ⚭8 contributors   ☯almost 6 years old  
  • VerificationExcellence/SystemVerilogReference

    training labs and examples

    ☕SystemVerilog   ★76 stars   ⚠0 open issues   ⚭1 contributors   ☯over 4 years old  
  • lowRISC/lowrisc-chip

    The root repo for lowRISC project and FPGA demos.

    ☕SystemVerilog   ★241 stars   ⚠16 open issues   ⚭2 contributors   ☯over 3 years old  
  • intel/fpga-partial-reconfig

    Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow

    ☕SystemVerilog   ★31 stars   ⚠0 open issues   ⚭2 contributors   ☯about 2 years old