Want to take your software engineering career to the next level? Join the mailing list for career tips & advice Click here

fpga-partial-reconfig

Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow

Subscribe to updates I use fpga-partial-reconfig


Statistics on fpga-partial-reconfig

Number of watchers on Github 31
Number of open issues 0
Main language SystemVerilog
Open pull requests 0+
Closed pull requests 0+
Last commit over 2 years ago
Repo Created almost 4 years ago
Repo Last Updated over 2 years ago
Size 22.8 MB
Organization / Authorintel
Latest Releasev17.1.0_1
Contributors2
Page Updated
Do you use fpga-partial-reconfig? Leave a review!
View on github
Book a Mock Interview With Me (Silicon Valley Engineering Leader, 100s of interviews conducted)
Software engineers: It's time to get promoted. Starting NOW! Subscribe to my mailing list and I will equip you with tools, tips and actionable advice to grow in your career.
Evaluating fpga-partial-reconfig for your project? Score Explanation
Commits Score (?)
Issues & PR Score (?)
fpga-partial-reconfig list of languages used
fpga-partial-reconfig latest release notes
v17.1.0_1 Release notes for 17.1.0_1 release

Intel® FPGA Partial Reconfiguration Design Flow

Release Notes Version v17.1.0_1

This release has been verified using Intel Quartus® Prime Pro Edition Software Version 17.1.0 Build 240

Related Links:

  • Main project page : https://01.org/fpga-partial-reconfig
  • Github repository : https://github.com/01org/fpga-partial-reconfig
  • Intel FPGA website: http://www.altera.com

Key Features of Partial Reconfiguration in Quartus Prime Pro Edition v17.1.0

The Intel FPGA Partial Reconfiguration Design Flow release version v17.1.0_1 includes the following new features and enhancements:

  • Intel Stratix 10 Traditional PR
    • New Stratix 10 PR tutorial for the Stratix 10 GX Development kit
      • Includes all sources files and application note
  • Intel Stratix 10 Traditional Hierarchical PR
    • New Stratix 10 HPR tutorial for the Stratix 10 GX Development kit
      • Includes all sources files and application note
  • Intel Stratix 10 Static Update PR
    • New Stratix 10 SUPR tutorial for the Stratix 10 GX Development kit
      • Includes all sources files and application note
  • Intel Arria 10 Static Update PR
    • New Arria 10 SUPR tutorial for the Arria 10 GX Development kit
      • Includes all sources files and application note
  • Intel Arria 10 Traditional PR
    • Updated version of the Arria 10 PR tutorial for the Arria 10 SoC Development kit
      • Includes all sources files and application note
    • Updated Arria 10 PR tutorial for the Arria 10 GX Devlopment kit
      • Includes all sources files and application note
    • Updated Arria 10 PR over PCIe reference design for the Arria 10 GX Development kit
      • Includes all sources files and application note
      • Includes PCIe Linux driver with upstreamed components and example host utility
  • Arria 10 Hierarchical PR
    • Updated Arria 10 HPR tutorial for the Arria 10 SoC Development kit
      • Includes all sources files and application note
    • Updated Arria 10 HPR tutorial for the Arria 10 GX Devlopment kit
      • Includes all sources files and application note
    • Updated Arria 10 HPR over PCIe reference design for the Arria 10 GX Development kit
      • Includes all sources files and application note
      • Includes PCIe Linux driver with upstreamed components and example host utility
  • Linux Driver
    • Updated FPGA-PCIe driver for PCIe attached FPGAs. The provided example host program demonstrates how easy it is to access the FPGA region's address space from user-level program.

Linux driver files are licensed under GPL2. Unless otherwise stated, all files are licensed under the terms of the MIT Open Source license. See the file named LICENSE in the root of the release for complete details.

v17.0.0_1 Release notes for 17.0.0_1 release

Intel® FPGA Partial Reconfiguration Design Flow

Release Notes Version v17.0.0_1

This release has been verified using Intel Quartus® Prime Pro Edition Software Version 17.0.0 Build 290

Related Links:

  • Main project page : https://01.org/fpga-partial-reconfig
  • Github repository : https://github.com/01org/fpga-partial-reconfig
  • Intel FPGA website: http://www.altera.com

Key Features of Partial Reconfiguration in Quartus Prime Pro Edition v17.0.0

The Intel FPGA Partial Reconfiguration Design Flow release version v17.0.0_1 includes the following new features and enhancements:

  • Intel Arria 10 Traditional PR
    • Signal Tap Debugging now supported for simultaneous acquisition of static and PR regions
    • Simulation of Partial Reconfiguration using RTL or PR simulation models of personas
    • Updated version of the Arria 10 PR tutorial for the Arria 10 SoC Development kit
      • Includes all sources files and application note
    • Updated Arria 10 PR tutorial for the Arria 10 GX Devlopment kit
      • Includes all sources files and application note
    • New Arria 10 PR over PCIe reference design for the Arria 10 GX Development kit
      • Includes all sources files and application note
      • Includes PCIe Linux driver with upstreamed components and example host utility
  • Arria 10 Hierarchical PR
    • Hierarchical PR allows you to create a PR region within an existing PR region
    • New Arria 10 HPR tutorial for the Arria 10 SoC Development kit
      • Includes all sources files and application note
    • New Arria 10 HPR tutorial for the Arria 10 GX Devlopment kit
      • Includes all sources files and application note
    • New Arria 10 HPR over PCIe reference design for the Arria 10 GX Development kit
      • Includes all sources files and application note
      • Includes PCIe Linux driver with upstreamed components and example host utility
  • Linux Driver
    • New FPGA-PCIe driver for PCIe attached FPGAs. Features an up-streamed driver for the Arria 10 Partial Reconfiguration Controller IP. The provided example host program demonstrates how easy it is to access the FPGA region's address space from user-level program.

Linux driver files are licensed under GPL2. Unless otherwise stated, all files are licensed under the terms of the MIT Open Source license. See the file named LICENSE in the root of the release for complete details.

v16.1.0_2 Release notes for 16.1.0_2 release

Intel® FPGA Partial Reconfiguration Design Flow

Release Notes Version v16.1.0_2

This release has been verified using Quartus Prime Pro Edition Software Version 16.1.0 Build 196

Related Links:

  • Main project page : https://01.org/fpga-partial-reconfig
  • Github repository : https://github.com/01org/fpga-partial-reconfig
  • Intel FPGA website: http://www.altera.com

New Features and Enhancements:

The Intel FPGA Partial Reconfiguration Design Flow release version v16.1.0_2 includes the following new features and enhancements:

  • Updated Arria 10 PR tutorial for the Arria 10 SoC Devlopment kit to use the production device in the QSF files
  • Application note for the Arria 10 PR tutorial using the Arria 10 GX Devlopment kit

Unless otherwise stated, all files are licensed under the terms of the MIT Open Source license. See the file named LICENSE in the root of the release for complete details.

Other projects in SystemVerilog
Powered by Autocode - Instant Webhooks, Scripts and APIs
Autocode logo wordmark