|Number of watchers on Github||55|
|Number of open issues||1|
|Open pull requests||0+|
|Closed pull requests||0+|
|Last commit||about 6 years ago|
|Repo Created||over 6 years ago|
|Repo Last Updated||over 1 year ago|
|Organization / Author||stiggy87|
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A Bitcoin miner for the Zynq chip utilizing the Zedboard.
The main goal of this is a proof-of-concept of making the Zedboard a fully functional Bitcoin miner for the open source community.
The basic design is to utilize the ARM dual core processor to handle communication to a pool and act as an arbiter for the miners. Utilizing AXI4 capabilities, it will be able to communicate with the programmable logic (PL) with ease.
A fully functional Zynq Bitcoin Miner. Since not everything about it are currently defined below are specifications:
Productizing- Each part of this system should be able to stand on its own, which allows anyone to create their own Zynq miner, or modify the current one with better results.
The SHA256 algorithm will be created in Vivado HLS is a High-Level Synthesis tool provided by Xilinx. The tool will then be able to output a valid IP to use within the design itself, but it does provide the HDL in case a user wants to make minor tweaks to the code (but it will be invalidated if it is regenerated).
Currently, all HLS related code is generated using the Vivado HLS 2012.4 30-day trial license provided by Xilinx.
FAQ - https://github.com/stiggy87/ZynqBTC/wiki/FAQ