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SystemVerilogReference

training labs and examples

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Statistics on SystemVerilogReference

Number of watchers on Github 76
Number of open issues 0
Main language SystemVerilog
Open pull requests 0+
Closed pull requests 0+
Last commit about 3 years ago
Repo Created over 6 years ago
Repo Last Updated over 2 years ago
Size 50 KB
Organization / Authorverificationexcellence
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This repository contains examples and sample short projects that can be used to learn basic concepts of functional verification using SystemVerilog

You can browse the code freely. If you want to clone a local copy - you need to first install git and then do following on a git bash shell (Refer http://readwrite.com/2013/09/30/understanding-github-a-journey-for-beginners-part-1 for basic github tutorial)

1) git clone https://github.com/verificationexcellence/SystemVerilogReference

There are two main sub directories in this repository 1) examples This directory contains several system verilog examples that you can refer through 2) project This directory will eventually contain short projects that takes a smaller design and builds a complete verification testbench around the same. For now - the only one project is a simple 2x2 port ethernet switch (dut and env)

For more specific details on how to run simulations - see the README files in examples/project sub-directories

Thanks VerificationExcellence Learn more www.verificationexcellence.in Contact verif.excellence@gmail.com for questions

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